代做app | scheme代写 | assignment | mips作业 – mips cache task

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代做app | scheme代写 | assignment | mips作业 – 这道题目是利用mips进行的编程代写任务, 是有一定代表意义的app/scheme/mips等代写方向, 该题目是值得借鉴的assignment代写的题目

ass代做 assignment代写 代写assignment

CMSC411  assignment 4
Summer 2022
On-time Due: June 30 (Thursday) by 6:00 PM
No Late Due

General instruction

  • Submit a PDF file to GradeScope You may edit the PDF file directly, scan your work on paper, or can also use an app (e.g., Scannable) to create a PDF file from photos of your work.
  • After uploading your work,dont forget to create mappingbetween questions and your answers. 5 points will be deducted if mapping is not or incorrectly given.
  • Unless specified, all questions will be graded.
  • Unless specified,justify your answers always.If justifications are missing or do not show reasonably how your answers are derived, 0 points will be assigned regardless of the correctness of the answers.
  • Writeneatlyincaseyouwriteyouranswersonpaper.Especially, for table completion questions, if your answers are not given neatly in well-drawn tables, the answers wont be graded.It is also recommended to print this file and put your answers on the printout.
  • This assignment must be done by yourself without any unauthorized assistance.Write your name and numeric student ID in the space below, and put your signature after reading the pledge statement.

Name:

SID (Numeric):

I pledge my honor that all parts of this assignment were done by me individually and
without any unauthorized assistance or collaboration with others.

Signature:

DO NOT SHARE THE QUESTIONS ON-/OFF-LINE.

Q1.Virtual Memory

Consider a machine with a Virtual Memory system with a 64-bit virtual address space per process, a
40-bit physical address, and a page size of 16KB.
(a) What is the total size of the page table for a process in bits, if there are 3 check bits (valid, dirty,
recentlyUsed) per page?
(b) (continued from the previous question) If the machine has 16GB of physical memory, what frac-
tion of the pages can reside in memory at any point in time?
(c) An approach to deal with the problem that arises from the large number of virtual pages and the
relatively small number of physical frames, is to store only a single page table entry per physical
frame. This approach is calledinverted page table.
In this design, the page table is indexed by the physical frame number instead of virtual page
number - i.e., physical frame number is used to look up (or locate) an entry in this table, and each
entry contains the matched virtual page number, a process ID (PID) associated with the virtual
page and check bits. A VPN and PID combination will be mapped to a physical frame number
by a function and the physical frame is used for the virtual page.
In the inverted page table design described above, what is the size of the inverted page table for
the virtual memory system in the previous question? Assume that a 10-bit PID and 4 check bits
are stored with the virtual page number.

(d) A simple scheme to translate a virtual page number to a physical frame number using an inverted page table is to search the table sequentially from the beginning of the table. If the virtual page number is matched with an entry, the index of the match is the physical frame number for the virtual page number. If there is no match, it is a page fault. This scheme looks very expensive because of the sequential search. Can you think of any better idea (i.e., a better mapping function) to maintain the inverted page table? Explain your idea. Just a few short sentences that explain the idea are enough.

Q2.Virtual Memory

Suppose that we have a machine with the following virtual/physical memory system organization.
  • The lowest virtual memory address:0x
  • The highest virtual memory address:0xFFFF
  • Virtual Page (and physical frame) size: 256 bytes (i.e., the page offset takes 8 bits)
  • The physical memory can hold 16 frames.
Based on the configuration above, answer the following questions. Assume that there is no unused bits
in a virtual memory address.
Dont forget to justify your answers  no need to be lengthy.
(a) Assuming a single-level page table, how many entries does the page table have?
(b) What is the number of bits used for a physical address?
(c) What is the number of bits used for a virtual page number?
More questions in the next page.
VPN valid PFN (in hex)
0 0 A
1 1 5
2 1 C
3 1 8
4 1 2
5 0 7
6 1 1
7 1 B
8 0 3
Table 1: Page table (partial view)

(d) Table 1 shows a partial page table. If the CPU references the virtual address0x04AA. What would be the physical memory address for the virtual address?

Q3.Cache

(a) Assume instruction execution in the simple  mips 5-stage pipeline, other than loads, is ideal 
i.e., 1 cycle per instruction. If an average CPI for load is 2.5 cycles total, and 30% of instructions
are loads, what is the average CPI (cycles per instruction) of the machine?
(b) Assume a two level cache with a 99% hit rate in L1 and an 85% hit rate in L2. Hits in L1 take 2
cycles, while hits in L2 take 10 cycles. A miss in both caches then goes to memory, which takes
100 cycles. What is the average access time for this memory system, in cycles?

Q4.Cache and Virtual Memory

We discussed in class that increasing block size can improve the hit rate (due to spatial locality), but
transfer time also increases. Given the cache organizations below, compute the miss penalty and the
AMAT in the following questions. Both designs have only one cache level.
Assume that the hit time is 1 cycle for both caches and that the memory accesses take 10 cycles for a
8-byte data transfer and needs 2 more cycle for every 8-byte additional transfer.
Write your answer in the boxes and show your work. No point will be given if only numeric values are
given in the boxes.
Cache A Cache B
Block Size 16 Bytes 32 Bytes
Miss Rate 5% 3%
(a) What is themiss penaltyfor Cache A and B, respectively? Give your answer incycles.
Cache A: Cache B:
(b) What is the average memory access time (AMAT) for Cache A and B, respectively? Give your
answer incycles.
Cache A: Cache B:
(c) The following code will be run on a machine with Cache A. Assume that:
  • Cache A is a write-back cache.
  • integertakes 4 bytes.
  • the highest memory address is0x7FFFFFFF(virtual address). That is, the memory address 0x80000000or higher does not store user program data.
  • the variable declared first is stored at the highest possible memory address.
  • the local variables are stored consecutively (in the downwards direction) on the stack and must be byte-aligned.
  • the page size is 4096 bytes
  • the virtual page number part of the virtual address wont be used for cache indexing.
  • variables are accessed by load and store instructions. int main(){ int i = 0, j = 1; char c1 = 65, c2 = 97; int k = 10;
printf("%d", i + j + k + c1 + c2);
return 0;
}
What is the number of cycles used for accessing cache/memory during the execution of the code?
Ignore the time to fetch instructions.
Cache A:

(d) (continued from the previous question) Assuming that the cache has 8 sets, what is the index value(s) of the block accessed in the previous question?

Index value: