HW 4 : Memory
代做report | arm代写 | 代写assignment | 代做mips – 本题是一个利用mips进行练习的代做, 对mips的流程进行训练解析, 涵盖了report/arm/mips等程序代做方面, 这个项目是assignment代写的代写题目
Due Dec. 5 , 20 20 , 11:5 5 pm
If you have questions, use the piazza forums (and professor/TA office hours) to obtain assistance.
Task:
There are 2 parts to this assignment: part 1: written exercises for Ch 5 ; part 2: Cache simulation using MARS. Basic rules regarding assignment implementation and submission:
- Total points of this assignment: 100.
- Team Allowed. Maximum 2 per Team . You should be able to specify your team on gradescope. To be safe, include names and G#s of group members in ALL submitted files.
Submission Instructions
- Submit to gradescope . A link to gradescope is available from Blackboard. There will be two assignments on gradescope, one for part 1 and one for part 2.
- For both parts, follow the submission instruction from gradescope. You will need to upload PDF files and specify which page we can find your answer. Make sure your answer is legible.
- Plagiarism is not permitted in any form. I enforce the university honor code.
Part 1. Written Exercise for Memory ( 6 0%) Notes:
- **A large portion of (or all) points will be taken off if you do not include required details in ** your answer. You must show steps to justify your answer.
- Answers must be legible , especially if you scan to generate your .pdf. 1. (10 pts) Explain how a 32-bit byte memory address should be divided into Tag/Index/Offset fields for each of the cache configurations below. Note : 1KB = 2^10 bytes. You must explain how many bits to assign to each field and the ordering of the three fields. **You get at most 50% of the ** credit if you give the length of each field without an explanation. 1.1. A fully associative cache with cache block size = 8 bytes and cache size = 512KB. 1.2. A direct-mapped cache with cache block size = 8 bytes and cache size = 512KB. 1.3. A four-way set associative cache with cache block size = 8 bytes and cache size = 512KB. 2. (10 pts) Calculate AMAT consider the following features:
- L1 cache hit time: 1ns, L1 cache miss rate: 20%
- A miss from L1 cache results in an access to L2 cache with the following assumptions: o L2 cache hit time: 3ns o L2 cache miss rate: 10%
- A miss from L2 cache results in a main memory access with an additional penalty time of 100ns
3. (10 pts) Consider a direct-mapped cache with a total size of 4 blocks. Given the initial cache status as below, fill the table for the given sequence of accesses (given as Index/Tag pairs in hexadecimal). Also fill the final cache table to describe the final cache status after the sequence of accesses. Assume that 0 means an invalid block. 4. ( 5 pts) Suppose a virtual memory has the size of a physical/virtual page to be 4KB (4*2^10 byte). Translate the following virtual addresses into VPNs (Virtual Page Number): 0x52000, 0x12348, 0x1ABCE, 0x0B36C. Also briefly explain how you translate. 5. ( 25 pts) Virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. The table must be updated with accesses. Assume the following configurations:
- Page table is indexed by VPN (virtual page number): row 0 is for VPN 0, etc.
- Assume initially the largest PPN (physical page number) is 8. If a new page needs to be brought in from the disk, always assign the next physical page number to it.
- TLB is fully associative with 4 entries and true LRU replacement
Fill the table below for a sequence of virtual addresses (given as VPNs in the table). For each address,
determine whether it is a TLB miss/hit, and (if it is a TLB miss) whether it is a page table hit/page
fault. Show how TLB is updated for every access as well as the final Page Table.
Initial Page Table: (all other entries are invalid) Index (VPN)
Valid Physical Page Number or
in Disk
0 1 5
1 0 Disk
2 1 3
3 0 Disk
4 1 8
5 0 Disk
6 1 2
7 0 Disk
Initial TLB:
Valid Tag
(VPN)
Physical
Page
Number
LRU
(1 as most
recent)
1 0 5 2
1 2 3 1
1 4 8 3
0 3 5 4
Index Valid Tag
0
1
2
3
Index Valid Tag
0 1 0x 3570
1 0 0x400A
2 1 0x
3 0 0x
Access Index Tag Hit/Miss? Replacement?
(^1) 0 0x (^2) 0 0x 3600 (^3) 1 0x360A (^4) 3 0x (^5) 1 0x360A Initial cache Final cache
Final Page table: ( use as many rows as you need ) Index Valid Physical Page Number or in Disk 0 1 2 3 4 5 6 7 8 9
Address
(VPN)
TLB Hit/Miss; Page
table hit/ page fault
TLB
Valid Tag PPN LRU
0x
0x
0x
0x
0x 4
Zhong CS465/001 Fall 2020
Part 2. MARS Memory Simulation (40%)
For this assignment, you will use MARS Data Cache Simulator to check and compare cache performance for different cache configurations and better understand the memory behavior. W arm up :
- Read MARS Tutorial Part 2 Activity 1: Running the Data Cache Simulator tool
- Try Step 1-7 with the provided row_major.asm o Use default cache settings and observe the performance
Simulation : With the provided row_major.asm , simulate the following cache configurations. For each simulation, record the final hit rate at the end of the simulation. NOTE :
- Make sure the simulation always starts with an empty cache. You may need to reset the mips program and reset the tool before you can re-run it.
- Feel free to adjust the Run Speed slider to any speed anytime you want to.
Required configurations to simulate:
- Group 1, Directed-mapping: o Number of Blocks: 8, Cache block size: 1 word, LRU o Number of Blocks: 8, Cache block size: 2 words, LRU o Number of Blocks: 8, Cache block size: 4 words, LRU (this is the default setting) o Number of Blocks: 8, Cache block size: 8 words, LRU
- Group 2, Directed-mapping: o Number of Blocks: 4, Cache block size: 8 words, LRU o Number of Blocks: 8, Cache block size: 8 words, LRU o Number of Blocks: 16, Cache block size: 8 words, LRU
- Group 3, Directed-mapping: o Number of Blocks: 16, Cache block size: 2 words, LRU o Number of Blocks: 8, Cache block size: 4 words, LRU o Number of Blocks: 4, Cache block size: 8 words, LRU o Number of Blocks: 1, Cache block size: 32 words, LRU
- Group 4, Fully associative: o Number of Blocks: 8, Cache block size: 4 words, LRU o Number of Blocks: 8, Cache block size: 4 words, Random o Number of Blocks: 4, Cache block size: 8 words, LRU o Number of Blocks: 4, Cache block size: 8 words, Random
- Group 5: o Direct-mapping, Number of Blocks: 8, Cache block size: 8 words, LRU o Fully associative, Number of Blocks: 8, Cache block size: 8 words, LRU o N-way set associative, Number of Blocks: 8, Cache block size: 8 words, LRU, Set size: o N-way set associative, Number of Blocks: 8, Cache block size: 8 words, LRU, Set size: o N-way set associative, Number of Blocks: 8, Cache block size: 8 words, LRU, Set size: o N-way set associative, Number of Blocks: 8, Cache block size: 8 words, LRU, Set size:
Report : Write a report based on your simulation results.
- For every group, summarize the hit rate in one table or one histogram. Make sure to include labels and captions to present your data clearly.
- For every group, explain and discuss the difference you observe for the different configurations in a group: What is the change (hit rate increasing/decreasing)? What is the reason of the change (or no-change)?
Grading rubric:
- Data collected and presented clearly 25/
- Discussion/explanation of the data 15/