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2019-10-08

Instruction-Level Parallelism

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 assignment #5  Instruction-Level Parallelism

Objective: To calculate the performance of a program with dependent arithmetic instructions, by simulating the execution on (i) a simple 6 – stage pipeline architecture; (ii) a 6 – stage superpipeline architecture. The six stages are: Fetch Instruction (FI), Decode Instruction (DI), Calculate Operands (CO), Fetch Operands (FO), Execute Instructions (EI), and Write Output (WO).

Inputs:

  • Number of instructions in the program
  • Set of automatically numbered instructions containing arithmetic register assignments
  • Architecture to simulate program on (pipelined, superscalar)

Outputs:

  • The total cycle count for the program
  • A Gantt chart of the pipelined stages of the instructions

Specification: The program calculates the performance of a set of arithmetic register assignment statements and prints out the aligned pipelined instructions based on choosing from a menu of choices, where each choice calls the appropriate procedure:

1 ) Enter instructions
2 ) Calculate total cycle count on a 6-stage pipeline architecture
3 ) Calculate total cycle count on a 6-stage superpipeline architecture
4 ) Quit program

{Hint: to recognize data dependencies, store the register indices in a struct containing
fields for the destination register index, both source register indices, and the dependency
delay. A data dependency occurs when the destination register of instruction (i) is the
same as at least one of the source registers of instruction (i+k). The delay is calculated
based on the distance between instruction (i) and instruction (i+k), i.e. the value of k }

What to turn in:

  • The source code as a single C file uploaded to Canvas (http://canvas.csun.edu) by the deadline (-20% per consecutive day for late submissions, up to the 4th day).

Instruction-level parallelism

  1. Enter instructions
  2. Calculate total cycle count on a 6-stage pipeline architecture
  3. Calculate total cycle count on a 6-stage superpipeline architecture
  4. Quit program

Enter selection: 1 Enter total number of instructions: 5

  1. r0=r1+r
  2. r1=r0+r
  3. r2=r3+r
  4. r0=r2+r
  5. r3=r3+r

Instruction-level parallelism

  1. Enter instructions
  2. Calculate total cycle count on a 6-stage pipeline architecture
  3. Calculate total cycle count on a 6-stage superpipeline architecture
  4. Quit program

Enter selection: 2

Total cycles: 14 |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O|

Instruction-level parallelism

  1. Enter instructions
  2. Calculate total cycle count on a 6-stage pipeline architecture
  3. Calculate total cycle count on a 6-stage superpipeline architecture
  4. Quit program

Enter selection: 3

Total cycles: 13. |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O| |F_I|D_I|C_O|F_O|E_I|W_O|

Instruction-level parallelism

  1. Enter instructions
  2. Calculate total cycle count on a 6-stage pipeline architecture
  3. Calculate total cycle count on a 6-stage superpipeline architecture
  4. Quit program

Enter selection: 4