report | VHDL – VHDL


report | VHDL – 这个题目属于一个VHDL的代写任务, 是比较有代表性的VHDL等代写方向

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Kings College London 201 8

Kings College London
This paper is part of an examination of the College counting towards
the award of a degree. Examinations are governed by the College
Regulations under the authority of the Academic Board.


Degree Programmes BEng, MEng

Module Code 6 CCS3HAD Module Title

Examination Period May 2018 (Period 2)

Time Allowed 3 hours



Calculators Calculators may be used. The following models are permitted: Casio fx83 / Casio fx

Books & notes Books, notes and other written materials may not be brought into this examination.


Question One

(a) Write VHDL code for the circuit in Figure 1. Assume that the gate delays are negligible, and A, B C, and D are inputs while G is output of the circuit. i. Use concurrent statements. [ 5 marks]

ii. Use a process with sequential statements.
[ 5 marks]
Figure 1

(b) In the following VHDL code, A, B, C, and D are integers that are 0 at time 10 ns. If D changes to 1 at 20 ns, specify the times at which A, B, and C will change and the value they will take.

[ 6 marks]
Question One continues on the next page
Process (D)
A <= 1 after 5 ns;
B <= A+1;
C <= B after 10 ns;
end process;

(c) An M-N flip-flop responds to the falling clock edge as follows:

  • If M = N = 0, the flip-flop changes state.
  • If M = 0 and N =1, the flip-flop output is set to 1.
  • If M= 1 and N = 0, the flip-flop output is set to 0.
  • If M = N = 1, no changes of flip-flop state occurs.

The flip-flop is also cleared asynchronously if CLRn = 0. Write the VHDL module that implements the M-N flip-flop.

[ 9 marks]
[Total 25 marks]

Question Two

Design a multiplier that will multiply two 16-bit signed binary integers to give a 32-bit product. Negative numbers should be represented in 2s complement form. For this, first complement the multiplier and multiplicand if they are negative, multiply the positive numbers, and then complement the product if necessary. Design the multiplier so that after the registers are loaded, the multiplication can be completed in 16 clocks.

i. Draw a block diagram of the multiplier. Use a 4-bit counter to
count the number of shifts. (The counter will output a signal K=
when it reaches 15.) Define all conditions and control signals
used on your diagram.
[7 marks]
ii. Draw a state diagram for the multiplier control using a minimum
number of states (five states). When the multiplication is
complete, the control circuit should output a signal indication
completion, and then wait for ST = 0 before returning to state
[8 marks]
iii. Write a VHDL behavioural description of the multiplier without
using control signals.
[5 marks]
iv. Write a VHDL behavioural description using control signals.
[5 marks]
[Total 25 Marks]

Question Three

(a) We want to test a Mealy sequential circuit with one input (X) and one output (Z). The code should include the Mealy circuit as a component. Assume that Mealy circuit changes state on the rising edge of clock (CLK). Your test code should generate a clock with 100 ns period. The code should apply the following test sequence:

X = 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0

X should change 10 ns after the rising edge of CLK. Your test code should read Z at an appropriate time and verify that the following output sequence was generated:

Z = 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0

Then report an error if the output sequence from the Mealy circuit is incorrect; otherwise report sequence complete.

Complete the architecture below, for the tester. (Do not write the code for the Mealy component)

[ 10 marks]
Question Three continues on the next page
architecture test1 of tester is
component Mealy
-- sequential circuit to be test
-- Do NOT write code for the component
port (X, CLK: in bit; Z: out bit);
end component ;
signal XA: bit_vector (0 to 11) : = 011011011100
signal ZA: bit_vector (0 to 11) : = 100110110110

(b) In the below process, conditions for state transition are explained in using a case statement. In this code, state and nextstate are integers with a range of 0 to 2.

i. What should be included in the sensitivity list of the process
(what are signal1 and signal2)?
[5 marks]
ii. Explain why a latch would be created when this code is
[5 marks]
iii. Make changes in the code which would eliminate the latch.
[5 marks]
[Total 25 marks]
Process (signal1, signal2)
Case state is
When 0 => if X= 1 then nextstate <= 1;
When 1 => if X = 0 then nextstate <= 2;
When 2 => if X = 1 then nextstate <= 0;
End case;
End process;

Question Four

Suppose we are designing a traffic light controller for the intersection of street A and street B. Each street has traffic sensors, which detect the presence of vehicles approaching or stopped at the intersection. The S-a=1 means a vehicle is approaching on street A and S-b=1 means a vehicle is approaching on street B. Street A is a main street and has a green light until a car approaches on B. Then the lights changes, and B has a green light. After 50 seconds, the lights change back unless there is another car on street B and there is no car on street A, in which case the B cycle is extended for additional 10 seconds. If cars continue to arrive on street Ba and no car appears on street A, B continues to have green light. When A is green, it remains green at least 60 seconds and then the lights change only when a car approaches on B. Figure 2 shows the external connections to the controller. Three of the outputs (G-a, Y-a, and R-a) drive the green, yellow and red lights on street A and the other three (G-b, Y-b, and R- b) drive the green, yellow and red lights on street B.

Figure 2
i. Draw a Moore state diagram for this controller. [5 marks]
ii. Write the VHDL code for the traffic light controller. [10 marks]
iii. Design a testbench to simulate 4 different scenar ios in street A
and street B and test the traffic light controller for these four
scenarios. [10 marks]
[Total 25 marks]

Question Five

(a) Find a minimum set of tests that will test all single stuck-at-0 and stuck-at-1 faults in the circuit of Figure 3. For each test, specify which faults are tested for s-a-0 and for s-a-1. [8 marks]

Figure 3

(b) A(1 to 20) is an array of 20 integers. Write the VHDL code that finds the largest integer in the array (only write the part of code relevant to this question without the general declarations). i. Using a for l oop [ 4 marks]

ii. Using a while loop [ 4 marks]

(c) Write the VHDL code to represent the 4-to-1 multiplexer, assuming that there is an inherent delay in the multiplexer that causes the change in output to occur 10 ns after a change in input. i. Using a conditional signal statement [4 marks]

ii. Using a process and a case statement [5 marks]
[Total 25 marks]